ASIC Power Design Engineer V at Mercor

ASIC Power Engineer | $100–135/hr | Sunnyvale, CA | Full-Time Contract

Join a prestigious tech company's AR/VR division as a senior ASIC Power Engineer, driving power analysis and optimization for cutting-edge consumer hardware. This role sits at the intersection of machine learning and silicon design, offering the opportunity to shape next-generation products at scale.

Responsibilities

• Perform PPA optimization using Fusion Compiler.
• Conduct RTL and netlist-level power analysis.
• Develop scripts for report log post-processing, format conversion, data analysis, and information extraction.
• Set up, run, debug, and analyze ASIC flow reports spanning Synthesis, Physical Design, Power, and Timing.
• Implement design blocks at RTL and UPF levels.
• Document findings and communicate results clearly across engineering teams.

Required Qualifications

• 10+ years of experience as an ASIC Power Engineer, CAD Engineer, or Physical Design Engineer.
• Proficiency with power estimation tools, synthesis flows, and physical design fundamentals.
• Strong understanding of power trade-offs in design and back-end implementation.
• Hands-on scripting experience in Python, Tcl, and/or SystemVerilog.
• BS in Electrical Engineering, Computer Science, or equivalent experience.

Preferred Qualifications

• Experience with Synopsys tools (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence Joules.
• Python, Perl, or similar scripting for data post-processing.
• Proficiency with Excel or MATLAB for model fitting, data visualization, and analysis.
• Experience with low-power design methodologies including UPF power intent specifications.
• Background in Silicon Power Characterization and power profiling at IP/SoC level.

This is a W-2 contract role administered by Cincinnatus, an enterprise staffing partner. Employment, payroll, and benefits are managed by Cincinnatus, with placement directly within the client's engineering team.