Front-End RTL Design Engineer at Turing

Front-End RTL Design Engineer | Remote | Contractor, 2-month engagement

About the role

Turing builds hardware-engineering training data and benchmarks for frontier AI labs. In this role, you turn real RTL work into tasks that measure how well AI models design hardware. Each task includes a specification, a starting design, a reference solution, and the tests that grade it.

You will author RTL design, bug-fix, and PPA (power, performance, area) optimization tasks on real IP, graded with the same simulation, synthesis, and equivalence-checking flows used to tape out chips. Your specifications, reference solutions, and tests become the ground truth these models learn from, so they must hold up to the same scrutiny as a design going to tape-out.

Day-to-day work

• Author design tasks: turn real IP into precise RTL design, bug-fix, and PPA-optimization tasks with a specification, starting point, and reference solution that meets every requirement.
• Set the PPA bar: run commercial and open-source synthesis to establish area, power, and timing baselines, and set targets that reward real engineering.
• Prove correctness: build the hidden tests and equivalence checks a solution must pass.
• Break your own tasks: attack each task the way a model would (removed logic, constraint loopholes, untested corners) and close the gaps before it ships.

Requirements

• BS/MS in Electrical, Electronic, or Computer Engineering, or equivalent practical experience.
• 3+ years of front-end digital design on ASIC or FPGA projects, from RTL through synthesis.
• Fluent Verilog/SystemVerilog: microarchitecture, datapaths, FSMs, pipelines, FIFOs, clock-domain crossings, and clock gating.
• Hands-on logic synthesis with timing constraints; able to read timing and quality-of-results reports and know which RTL or constraint change moves area, timing, or power.
• Hands-on commercial synthesis (Cadence Genus, Synopsys Design Compiler/Fusion Compiler) or, for FPGA targets, AMD Vivado including Vitis HLS flows.
• Hands-on open-source synthesis with Yosys (directly or via OpenLane/LibreLane) and simulation with Icarus Verilog or Verilator (directly or under cocotb).
• Self-checking testbenches in cocotb (Python) or SystemVerilog, plus waveform-level debug.
• Python and Tcl scripting for flow automation; comfortable in Linux, Git, and Docker-based environments.

Engagement details

• Contractor assignment; no medical or paid leave provided.
• Minimum 40 hours per week, with a daily overlap of 4 hours with PST.
• Contract duration: 2 months (adjustable based on engagement).
• Fully remote.

Application process

• Technical interview.