RTL Design Engineer at Mercor

RTL Design / Verification Engineer | $100–175/hr | Remote (US & Canada)

Mercor is sourcing senior digital chip design and verification engineers to support an AI evaluation program focused on frontier silicon and chip-design workflows. This is a high-impact, full-time engagement starting the week of 04/23, targeting a duration of 3+ months. Strong contributors who can commit 40 hours per week will be prioritized.

Two parallel tracks are available — candidates may apply to either:

Track 1: RTL Design Engineer

Qualifications:

• 3–10 years of experience in digital RTL design
• Strong proficiency in Verilog / SystemVerilog
• Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, and bus protocols
• Experience with ASIC design flows: lint, synthesis, timing analysis, CDC, and DFT-aware design
• Familiarity with EDA tools for simulation, waveform debug, lint, CDC, synthesis, and timing analysis
• Experience leveraging LLM-based tools to accelerate chip design, RTL development, debug, documentation, or verification workflows
• Ability to write clear design documentation and communicate technical tradeoffs
• Experience debugging RTL issues using simulation logs and waveform viewers
• Strong collaboration skills across architecture, verification, and implementation teams

Preferred:

• AMBA protocols (AXI, AHB, APB)
• Background in CPU, GPU/ML accelerator, networking, memory subsystem, PCIe/high-speed IO, SoC interconnect, or low-power design
• Exposure to formal verification or SV/UVM-based design verification

Track 2: Design Verification Engineer

Qualifications:

• 3–10 years of experience in design verification
• Strong proficiency in SystemVerilog and UVM
• Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, and bus protocols
• Experience developing reusable verification components and testbench infrastructure
• Expertise in constrained-random verification, functional coverage, SVA assertions, and coverage closure
• Familiarity with EDA tools for simulation, waveform debug, coverage analysis, formal verification, and regression management
• Experience using LLM-based tools to accelerate verification, debug, test generation, documentation, or coverage analysis
• Ability to write clear verification plans, debug reports, and technical documentation

Preferred:

• AMBA protocols (AXI, AHB, APB)
• Background in CPU, GPU/ML accelerator, networking, memory subsystem, PCIe/high-speed IO, SoC interconnect, or low-power verification
• Experience with reusable verification IP, scoreboards, reference models, and coverage-driven regression flows

Engagement Details

• Location: Fully remote — open to candidates in the US and Canada only
• Commitment: Full-time, 40 hours per week required
• Duration: ~3+ months, starting the week of April 23rd
• Rate: $100–$175/hr depending on experience and track